The present invention relates to a method of forming an isolation layer in a semiconductor device and, more particularly, to a method of forming an isolation layer in a semiconductor device, wherein moats caused by a high density plasma (HDP) deposition characteristic are filled to eliminate a factor causing a generation of subsequent voids.
As semiconductor devices become more highly-integrated, processes for forming isolation layers become more difficult. Accordingly, an isolation layer is formed by means of a STI (shallow trench isolation) method in which a trench is formed on a semiconductor substrate and the trench is then filled. In the meantime, in the various STI methods, the method in which a tunnel insulating layer, a polysilicon layer, and a hard mask layer are laminated on a semiconductor substrate, are then sequentially etched to form a trench, and an oxide layer is formed on an overall structure to fill the trench, have been applied to semiconductor devices, such as NAND-type flash memory devices. In highly-integrated devices, however, as compared with a width of entrance of the trench, the depth of the trench is large, and it is thus more difficult to completely gap-fill the trench with a conventional high density plasma (HDP) oxide layer without generating voids due to the large aspect ratio, thus making it difficult to form an isolation layer. In order to solve the above problem, research in the material used for gap-filling the trench without generating voids has been actively conducted.
As one of the methods conceived to solve the above problem, the method in which a trench is completely gap-filled by means of polysilazane (PSZ), which is a spin on dielectric (SOD) material has been employed. In this method, PSZ-based material having sufficient flowability, being capable of filling a narrow trench, is applied and deposited to form an oxide layer. The oxide layer is then cured and planarized by a chemical mechanical polishing (CMP) process.
However, since polysilazane (PSZ) material typically contains a large quantity of impurities and moisture, the isolation layer formed from only polysilazane (PSZ) material is favorable to a gap-fill, but tends to be detrimental to the reliability of the device. Accordingly, a wet etch back process is performed to reduce the thickness of the polysilazane (PSZ) layer to secure a subsequent gap-fill margin, and a high density plasma (HDP) oxide layer with a certain thickness is then formed. However, due to a characteristic of the process for forming the high density plasma (HDP) oxide layer, on the remainder of the semiconductor substrate except a central region, the high density plasma (HDP) oxide layer is thinly formed on a side wall of a trench adjacent to an edge region, and so a moat is generated by the above asymmetrical deposition. After the high density plasma (HDP) oxide layer is formed, a portion of the high density plasma (HDP) oxide layer is etched through a wet etch back process, and the high density plasma (HDP) oxide layer is then additionally and thickly formed. At this time, void is formed generated in a portion on which the moat is formed.
In a case where the void is formed in the oxide layer, in the process for removing an isolation nitride layer performed after a subsequent chemical mechanical polishing (CMP) process performed for forming the isolation layer, a side wall of a conductive layer for a floating gate is exposed by an etchant so that the conductive layer for a floating gate can be severely lost. In this state, if PCL (Peri Close) mask and etching processes for maintaining an effective field height (EFH) of a peripheral region are performed, the conductive layer for a floating gate is partially stripped due to an attack on the conductive layer for a floating gate. This phenomenon reduces an area of the floating gate to decrease a coupling ratio of a cell, so an operation characteristic of the semiconductor device becomes lowered.